The antifuse is less than 100 nm diameter and programmed fuses are not visible when viewed from the top of the die. Security-wise, the technology is hard to beat determining the on-off state of an antifuse requires physically delving into the chip. Interconnect lines are connected using a programming impulse to short out the antifuse dielectric. The antifuse programming switch uses a very silicon-efficient dielectric embedded within the metal layers 2 and 3 of the chip, thus taking up virtually no overhead compared to the SRAM switch. Antifuse FPGAs are high-speed, 'live-on-power-up' devices that are based on a fine-grained, ASIC-like four-input/one-output logic structure comprising NAND and NOR gates with an associated flip-flop. Some of the above problems are addressed by antifuse technology. They are worried that devices could be cloned by copying a bitstream sourced to the FPGA either by a nonvolatile boot PROM or a microprocessor. For applications such as line interface cards that need to be 'live-on-power-up', SRAM FPGAs have to be isolated with extra circuitry so that they appear 'live' during their boot-up process.Īs the value of the designs implemented in FPGAs increases, security limitations of SRAM-based FPGAs are an area of concern for some users. A boot device adds to the cost and complicates both system and board design compared to a single gate array. Other sticking points surrounding the use of SRAM FPGAs include their nonvolatility (they are not 'live-on-power-up') and their requirement for an associated boot PROM to hold the circuit configuration. Timing closure can take many iterations, adding weeks in some cases to the expected design cycle. Moreover, because the SRAM FPGAs have a more complex, coarser-grained architecture than the two-input/one-output NAND structure of a gate array, achieving timing convergence is more time-consuming because designs do not map in a straightforward fashion. Clearly, the switches constitute a substantial silicon overhead compared to a gate array with a similar logic capacity. Each SRAM switching element typically comprises six transistors and there will be millions of these switches in a large device. The lines of interconnect, linking the logic blocks are programmed using SRAM-based switches. SRAM FPGAs are built around a complex logic block structure based on look-up-tables (LUTs) tied to flip-flops. But because of their complicated architectures they are rather inefficient in their use of silicon. These chips have the great advantage of being reprogrammable and In-System-Programmable. The dominant programmable logic technology on the market is the SRAM-based FPGA. There are also niggling issues surrounding FPGAs in terms of nonvolatility, security and ease of design. But FPGA device costs at densities over 50 K ASIC gates remain a problem they tend to be considerably higher than equivalent gate arrays. Now, many of today's FPGA offerings can easily accommodate designs in the 50 K-300 K ASIC gate sweet spot of the ASIC market. A few years back, FPGA logic densities lagged significantly behind those of ASICs, limiting their use as replacement devices. The lack of NRE charges coupled with the flexibility to buy and program devices as and when required, have always been big selling points for FPGAs. Actel's new ProASIC PLUS family fills the gap between 50 000 and 300 000 ASIC gates, offering for the first time a true gate array alternative in a nonvolatile, In-System-Programmable FPGA. For higher gate-count designs, today's FPGAs can still be a compromise. Gate arrays or ASICs of 50000 ASIC gates and below have been largely superseded by FPGAs. Field-programmable gate array (FPGA) technology has grown in popularity over recent years to a point where FPGAs are used in preference to ASICs in many applications.
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